module ram #(
        parameter W=16
)(
	input		CLK_I,
	input		RST_I,
	input		CYC_I,
	input		STB_I,
	input		WE_I,
	output		ACK_O,
	input	[W-1:2]	ADR_I,
	input	[3:0]	SEL_I,
	input	[31:0]	DAT_I,
	output	[31:0]	DAT_O,

        input           i_read_instr,
	input	[W-1:2]	i_addr_instr,
	output	[31:0]	o_data_instr
);

wire	i_clk = CLK_I;
wire	i_rst = RST_I;

wire	write_data = CYC_I & STB_I &  WE_I;

reg	ack_instr;

always @(posedge i_clk) begin
	if (i_rst) ack_instr <= 1'b0;
	else ack_instr <= 1'b1;
end

reg  ack_r;
assign ACK_O = ack_r;

wire [31:0] dat1;
reg  [31:0] dat1_r;
assign DAT_O = dat1_r;

reg [1:0] a;

always @(posedge CLK_I) begin
        if (RST_I) begin
                a <= 2'b10;
                ack_r <= 1'b0;
                dat1_r <= 32'b0;
        end else begin
                if (CYC_I & STB_I & ~ack_r) begin
                        a <= {1'b0, a[1]};
                        ack_r <= a[0];
                end else begin
                        a <= 2'b10;
                        ack_r <= 1'b0;
                end
                dat1_r <= dat1;
        end
end

`ifdef USE_GENERIC_LIB
generic_blk_mem #(.DEPTH(W-2))
`else
blk_mem_gen_v7_3
`endif
u_ram(
	.clka(i_clk),
	.wea({4{write_data}} & SEL_I),
	.addra(ADR_I),
	.dina(DAT_I),
	.douta(dat1),
	.clkb(i_clk),
        .enb(i_read_instr),
	.web(4'b0),
	.addrb(i_addr_instr),
	.dinb(32'b0),
	.doutb(o_data_instr)
);

endmodule
